View 74ALVCH16500_291983.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
74ALVCH16500 18-bit universal bus transceiver (3-State)
Product specification Supersedes data of 1998 Aug 31 IC24 Data Handbook 1998 Sep 24
Philips Semiconductors
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ALVCH16500
FEATURES
* Complies with JEDEC standard no. 8-1A * CMOS low power consumption * Direct interface with TTL levels * Current drive 24 mA at 3.0 V * All inputs have bushold circuitry * Output drive capability 50 transmission lines @ 85C * MULTIBYTETM flow-through standard pin-out architecture * Low inductance multiple VCC and ground pins for minimum noise
and ground bounce
DESCRIPTION
The 74ALVCH16500 is a high-performance CMOS product. This device is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is High. When LEAB is Low, the A data is latched if CPAB is held at a High or Low logic level. If LEAB is Low, the A-bus data is stored in the latch/flip-flop on the High-to-Low transition of CPAB. When OEAB is High, the outputs are active. When OEAB is Low, the outputs are in the high-impedance state. Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The output enables are complimentary (OEAB is active High, and OEBA is active Low). To ensure the high impedance state during power up or power down, OEBA should be tied to VCC through a pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25C; tr = tf = 2.5ns SYMBOL tPHL/tPLH CI/O CI CPD PARAMETER Propagation delay An, Bn to Bn, An Input/output capacitance Input capacitance Power dissipation capacitance per latch dissi ation ca acitance er VI = GND to VCC1 Outputs enabled Outputs disabled CONDITIONS VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF TYPICAL 3.1 2.9 8.0 4.0 21 3 UNIT ns pF pF pF F
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + S (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL x VCC2 x fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES 56-Pin Plastic TSSOP Type II TEMPERATURE RANGE -40C to +85C OUTSIDE NORTH AMERICA 74ALVCH16500 DGG DWG NUMBER SOT364-1
1998 Sep 24
2
8533-2125 20079
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ALVCH16500
PIN CONFIGURATION
OEAB LEAB A0 GND A1 A2 VCC A3 A4 A5 1 2 3 4 5 6 7 8 9 10 56 GND 55 CPAB 54 A0 53 GND 52 B1 51 B2 50 VCC 49 B3 48 B4 47 B5 46 GND 45 B6 44 B7 43 B8 42 B9 41 B10 40 B11 39 GND 38 B12 37 B13 36 B14 35 VCC 34 B15
PIN DESCRIPTION
PIN NUMBER 1 2 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26 4, 11, 18, 25, 29, 32, 39, 46, 53, 56 7, 22, 35, 50 27 28 30 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31 55 SYMBOL OEAB LEAB NAME AND FUNCTION Output enable A-to-B Latch enable A-to-B
A0 to A17
Data inputs/outputs
GND VCC OEBA LEBA CPBA
Ground (0V) Positive supply voltage Output enable B-to-A Latch enable B-to-A Clock input B-to-A
GND 11 A6 12 A7 13
B0 to B17
Data inputs/outputs
A8 14 A9 15 A10 16 A11 GND A12 17 18 19
CPAB
Clock input A-to-B
BUS HOLD CIRCUIT
VCC
A13 20 A14 VCC A15 21 22 23
Data Input A16 24 GND A17 OEBA 25 26 27 33 B16 32 GND 31 B17 30 CPBA 29 GND
To internal circuit
LEBA 28
SW00080
SW00044
1998 Sep 24
3
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ALVCH16500
LOGIC SYMBOL
3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 1 2 55 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 OEAB LEAB CPAB B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 OEBA LEBA CPBA 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 27 28 30
LOGIC SYMBOL (IEEE/IEC)
OEAB CPAB LEAB 1 56 2 EN1 2C3 C3 G2 OEAB CPBA LEBA 27 30 28 EN4 5C6 C6 G5 A0 3 3D 4 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 1 1 1 6D 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 54 B0
SW00081
SW00082
1998 Sep 24
4
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ALVCH16500
LOGIC DIAGRAM (one section)
OEAB CPBA LEBA CPAB LEAB OEBA
C1
C1 Bn
An
1D
1D
C1
C1
1D 18 IDENTICAL CHANNELS
1D
SW00090
FUNCTION TABLE
INPUTS OEAB L H H H H H H H H LEAB H H H L L L L CPAB X X X X X H or L H or L An X H L h I h I X X OUTPUTS Bn Z H L H L H L H L Latch data & dis lay display Clock data & display dis lay Hold data & display dis lay Disabled Transparent OPERATING MODE
NOTE: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, and CPBA. H = High voltage level h = High voltage level one set-up time prior to the Enable or Clock transition L = Low voltage level I = Low voltage level one set-up time prior to the Enable or Clock transition NC= No Change X = Don't care Z = High Impedance "off" state = High-to-Low Enable or Clock transition
1998 Sep 24
5
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ALVCH16500
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL PARAMETER DC supply voltage 2.5V range (for max. speed performance @ 30 pF output load) VCC DC supply voltage 3.3V range (for max. speed performance @ 50 pF output load) DC Input voltage range DC output voltage range Operating free-air temperature range Input rise and fall times VCC = 2.3 to 3.0V VCC = 3.0 to 3.6V CONDITIONS MIN 2.3 3.0 0 0 -40 0 0 MAX 2.7 V 3.6 VCC VCC +85 20 10 V V C ns/V UNIT
VI VO Tamb tr, tf
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK VI IOK VO IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC in ut voltage input DC output diode current DC output voltage DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package -plastic thin-medium-shrink (TSSOP) For temperature range: -40 to +125 C above +55C derate linearly with 8 mW/K VI t0 For control pins1 For data inputs1 VO uVCC or VO t 0 Note 1 VO = 0 to VCC CONDITIONS RATING -0.5 to +4.6 -50 -0.5 to +4.6 -0.5 to VCC +0.5 "50 -0.5 to VCC +0.5 "50 "100 -65 to +150 600 V mA V mA mA C mW UNIT V mA
NOTE: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Sep 24
6
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ALVCH16500
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +85C MIN VIH HIGH level Input voltage VCC = 2.3 to 2.7V VCC = 2.7 to 3.6V LOW level Input voltage VCC = 2.3 to 2.7V VCC = 2.7 to 3.6V VCC = 2 3 to 3 6V; VI = VIH or VIL; IO = -100A 100A 2.3 3.6V; VCC = 2.3V; VI = VIH or VIL; IO = -6mA VO OH HIGH level output voltage VCC = 2.3V; VI = VIH or VIL; IO = -12mA VCC = 2.7V; VI = VIH or VIL; IO = -12mA VCC = 3.0V; VI = VIH or VIL; IO = -12mA VCC = 3.0V; VI = VIH or VIL; IO = -24mA VCC = 2 3 to 3 6V; VI = VIH or VIL; IO = 100A 2.3 3.6V; VCC = 2.3V; VI = VIH or VIL; IO = 6mA VOL LOW level output voltage VCC = 2.3V; VI = VIH or VIL; IO = 12mA VCC = 2.7V; VI = VIH or VIL; IO = 12mA VCC = 3.0V; VI = VIH or VIL; IO = 24mA II IOZ ICC ICC IBHL Input leakage current g 3-State output OFF-state current Quiescent supply current Additional quiescent supply current Bus hold LOW sustaining current VCC = 2 3 to 3 6V; 2.3 3.6V; VI = VCC or GND VCC = 2.7 to 3.6V; VI = VIH or VIL; VO = VCC or GND VCC = 2.3 to 3.6V; VI = VCC or GND; IO = 0 VCC = 2.3V to 3.6V; VI = VCC - 0.6V; IO = 0 VCC = 2.3V; VI = 0.7V2 VCC = 3.0V; VI = Bus hold HIGH sustaining current Bus hold LOW overdrive current Bus hold HIGH overdrive current 0.8V2 45 75 -45 -75 500 -500 -175 VCC*0.2 02 VCC*0.3 VCC*0.6 VCC*0.5 VCC*0.6 VCC*1.0 1.7 2.0 TYP1 1.2 V 1.5 1.2 1.5 VCC VCC*0.08 VCC*0.26 VCC*0.14 VCC*0.09 VCC*0.28 GND 0.07 0.15 0.14 0.27 0.1 0.1 0.2 150 - 150 0.20 0 20 0.40 0.70 0.40 0.55 5 10 40 750 A A A A A V V V V 0.7 V 0.8 MAX UNIT
VIL
IBHH IBHLO IBHHO
VCC = 2.3V; VI = 1.7V2 VCC = 3.0V; VI = VCC = 3.6V2 VCC = 3.6V2 2.0V2
A A A
NOTES: 1. All typical values are at Tamb = 25C. 2. Valid for data inputs of bus hold parts.
1998 Sep 24
7
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ALVCH16500
AC CHARACTERISTICS FOR VCC = 2.3V TO 2.7V RANGE
GND = 0V; tr = tf 2.0ns; CL = 30pF LIMITS SYMBOL PARAMETER WAVEFORM MIN Propagation delay An, Bn to Bn, An tPHL/tPLH Propagation delay LEAB, LEBA to Bn, An Propagation delay CPAB, CPBA to Bn, An 3-State output enable time OEBA to An 3-State output enable time OEAB to Bn 3-State output enable time OEBA to An 3-State output enable time OEAB to Bn Pulse width HIGH LEAB, LEBA Pulse width HIGH or LOW CPAB, CPBA Set-up time An, Bn to CPAB, CPBA Set-up time An, Bn to LEAB, LEBA Hold time An, Bn to CPAB, CPBA Hold time An, Bn to LEAB, LEBA Maximum clock frequency 1, 2 1.0 1.0 1.0 1.0 3 1.0 1.0 3 1.0 3.3 2 3.3 1.7 4 1.9 1.7 4 2.0 150 0.2 333 - - MHz 0.1 0.2 - - ns 2.0 0.1 - - ns 2.7 0.8 6.1 - ns 2.7 2.8 5.7 5.4 ns VCC = 2.5V 0.2V TYP1 3.1 3.6 3.7 3.1 MAX 5.2 6.2 6.6 6.2 ns ns UNIT
tPZH/tPZL
tPHZ/tPLZ
tW
tS SU
th
fMAX
NOTE: 1. All typical values are at VCC = 2.5V and Tamb = 25C.
1998 Sep 24
8
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ALVCH16500
AC CHARACTERISTICS FOR VCC = 3.0V TO 3.6V RANGE AND VCC = 2.7V
GND = 0V; tr = tf = 2.5ns; CL = 50pF LIMITS SYMBOL PARAMETER WAVEFORM VCC = 3.3V 0.3V MIN Propagation delay An, Bn to Bn, An tPHL/tPLH Propagation delay LEAB, LEBA to Bn, An Propagation delay CPAB, CPBA to Bn, An 3-State output enable time OEBA to An 3-State output enable time OEAB to Bn 3-State output disable time OEBA to An 3-State output disable tiime OEAB to Bn LE pulse width LEAB, LEBA to CPAB, CPBA LE pulse width HIGH or LOW CPAB, CPBA Set-up time An, Bn to CPAB, CPBA Set-up time An, Bn to LEAB, LEBA Hold time An, Bn to CPAB, CPBA Hold time An, Bn to LEAB, LEBA Maximum clock frequency 1, 2 1.0 1.0 1.1 1.0 3 1.0 1.0 3 1.5 3.3 2 3.3 1.3 4 1.4 1.3 4 1.5 150 0.1 340 1.8 150 0.1 333 MHz 0.3 -0.1 1.6 1.6 -0.2 0.3 ns 1.1 0.2 3.3 1.4 1.4 0.1 ns 3.2 0.9 5.0 3.3 3.6 0.7 ns 5.7 2.5 3.2 4.6 4.3 2.7 3.3 5.4 4.6 ns TYP1 2.9 3.1 3.3 2.8 MAX 4.2 4.9 5.5 5.2 MIN VCC = 2.7V TYP 3.1 3.4 3.8 3.3 MAX 4.7 5.5 6.6 6.2 ns ns UNIT
tPZH/tPZL
tPHZ/tPLZ
tW
tS SU
th
fMAX
NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25C.
1998 Sep 24
9
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ALVCH16500
AC WAVEFORMS
VCC = 2.3 TO 2.7 V RANGE 1. VM = 0.5 V 2. VX = VOL + 0.15V 3. VY = VOH - 0.15V 4. VI = VCC 5. VOL and VOH are the typical output voltage drop that occur with the output load. VCC = 3.0 TO 3.6 V RANGE AND VCC = 2.7 V 1. VM = 1.5 V 2. VX = VOL + 0.3V 3. VY = VOH - 0.3V 4. VI = 2.7 V 5. VOL and VOH are the typical output voltage drop that occur with the output load.
VI An, Bn INPUT GND tPHL VOH Bn, An OUTPUT VOL An, Bn INPUT VM tPLH VOH VM OUTPUT HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled VY VM OEAB INPUT VM OEBA INPUT VM
tPLZ VCC OUTPUT LOW-to-OFF OFF-to-LOW VOL tPHZ
tPZL
VM VX
tPZH
SW00085
Waveform 3. 3-State enable and disable times
Waveform 1. Input (An, Bn) to output (Bn, An) propagation times
GND
CPXX INPUT
VI
CPXX, LEXX INPUT VM GND
LEXX INPUT GND VOH An, Bn OUTPUT VOL
tW tPHL tPLH
NOTE: The unshaded areas indicate when the input is permitted to change for predictable output performance.
VM
Waveform 4. Data set-up and hold times for the An and Bn inputs to the LEAB, LEBA, CPAB and CPBA inputs
SW00084
Waveform 2. Latch enable input (LEAB, LEBA) and clock pulse input (CPAB, CPBA) to output (An, Bn) propagation delays and latch enable pulse width
1998 Sep 24
10
EEEEEEEEEE EEE E EEEEEEEEEE EEE E EEEEEEEEEE EEE E
VM th th tSU tSU VI VM
SW00083
VI
SW00093
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ALVCH16500
TEST CIRCUIT
VCC S1 2 * VCC Open GND
VI PULSE GENERATOR RT D.U.T.
VO
RL = 500
CL
RL = 500
Test Circuit for switching times DEFINITIONS
RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators.
SWITCH POSITION
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 < VCC
GND
VCC < 2.7V 2.7-3.6V
VI VCC 2.7V
SV00906
Waveform 5. Load circuitry for switching times
1998 Sep 24
11
Philips Semiconductors
Product specification
18-Bit Universal Bus Transceiver
74ALVCH16500
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
1998 Sep 24
12
Philips Semiconductors
Product specification
18-Bit Universal Bus Transceiver
74ALVCH16500
NOTES
1998 Sep 24
13
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ALVCH16500
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Date of release: 08-98 Document order number: 9397-750-04802
Philips Semiconductors
1998 Aug 31 14

▲Up To Search▲

Price & Availability of 74ALVCH16500

	To Download 74ALVCH16500 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .